`timescale 1ns/1ps

module hex8_tb();
	
	reg clk;
	reg rst_n;
	reg [31:0] data;
	wire [7:0] sel;
	wire [7:0] seg;

hex8 hex8_inst(
	.clk(clk),
	.rst_n(rst_n),
	.data(data),
	.sel(sel),
	.seg(seg)
);

	initial clk = 1;
	always #10 clk = ~clk;
	
	initial begin
		rst_n = 0;
		data = 32'h12345678;
		#201;
		rst_n = 1;
		#20_000_000;
		data = 32'habcdef01;
		#20_000_000;
		$stop;
	end

endmodule
